The present invention relates generally to semiconductor-based lasers, and more particularly, to Vertical Cavity Surface-Emitting Lasers (VCSELs).
Optical data communication systems provide an important way for transferring large amounts of data at high speeds. An important component in these optical data communication systems is an optical transceiver. On the transmission side, the optical transceiver functions to translate data in the form of electrical signals (e.g., digital information in the form of 1s and 0s) into optical signals that are suitable for transmission via a transmission medium (e.g., fiber optic cable). On the reception side, the optical transceiver converts the received optical signals back into data in the form of electrical signals. An important component in the optical transceiver design is the transmitter for transmitting optical data. Typically, the transmitter is implemented with a light emitting diode (LED) for megabit applications and a semiconductor laser diode for gigabit applications.
Semiconductor laser diodes were originally fabricated in a manner that provides an optical cavity formed parallel to the surface of the semiconductor wafer. In this structure, light is emitted from the edge of the wafer. Unfortunately, this structure does not lend itself to low cost xe2x80x9cmassxe2x80x9d manufacturing or to the cost-effective fabrication of two-dimensional arrays of laser diodes.
A new class of laser diodes is fabricated such that the optical cavity is formed perpendicular to the surface of the semiconductor wafer, and the light is emitted perpendicular to the surface. These laser diodes are commonly referred to as Vertical Cavity Surface-Emitting Lasers (VCSELs). A typical VCSEL consists of an active region which emits light and surrounding mirrors constructed from alternating layers of materials having different indices of refraction. These lasers are better suited for the fabrication of arrays and are widely utilized in optical data communication systems.
The lateral dimension of VCSELs is defined by confining the current flowing vertically in the VCSEL to a small area. Early designs utilized either etched mesa or ion-implanted regions to contain the current flow. However, these approaches are not satisfactory for small size devices. For the etched mesa approach, there is the problem of light scattering. For the implanted approach, there is the problem of optical confinement in the implanted structure.
In response to these shortcomings, a method for restricting the current flow and also for providing optical confinement was developed. This method utilizes an oxide aperture created by a wet oxidation process to convert one or more high aluminum content layers within the VCSEL structure to some form of aluminum oxide.
There are two main VCSEL structures that each has a different approach to form this current-restricting oxide aperture by oxidizing a single or multiple aluminum-containing layers in mirror stacks by using different surface topologies. A first type of prior art VCSELs uses a so-called mesa-type or pillar-type structure having a relatively tall etched xe2x80x9cpillarxe2x80x9d mesa, with a relatively small oxidation area, which enables it for high speed operations. One such mesa-type VCSEL is described in U.S. Pat. No. 5,493,577, entitled xe2x80x9cEfficient Semiconductor Light-Emitting Device and Method,xe2x80x9d by Choquette et al.
One problem with the mesa-type oxide-confined VCSELs is the nonplanar geometry encountered in fabricating such devices. In general, the bottom of the mesa has to be etched deep enough to get access to the oxide aperture forming layers, which is usually several microns below the original epitaxial surface (typically 4xcx9c7 xcexcm). To provide access to the layer being oxidized, the device is first etched to form a mesa structure with the edges of the various mirror layers exposed. The exposed edges are then subjected to a wet oxidation process. The oxidation process proceeds along the layer from the outer edge of an etched mesa toward the center of the mesa. The process is stopped prior to converting the entire layer, thereby leaving a small unoxidized area in the center of the mesa, which defines the laser aperture. The mesa-structure is generally more difficult to fabricate than the planar approach described hereinbelow.
A second problem is that these mesa-type structures requires a thick insulative filling (e.g., polyimide) in order to bridge the top metal contact and the metal bond pad, which can sit on the polyimide or on a semi-insulating substrate. Since the insulative layer has a thermal coefficient that is quite different from the thermal coefficient of the semiconductor layer, the polyimide layer tends to apply severe stress to the semiconductor during the both the fabrication process of and operation of the VCSEL. For example, when the device is subject to thermal or electrical stress, the differences in the thermal coefficient of the polyimide and the semiconductor layer can potentially cause the device to physically or structurally fail. Consequently, it has been a challenge from a manufacturing point of view to fabricate highly reliable and high speed oxide-confined VCSEL based upon the mesa-type structure.
The second type of prior art VCSELs features a planar topology. One such planar-type VCSEL is described in U.S. Pat. No. 5,896,408, entitled xe2x80x9cNear planar native-oxide VCSEL Devices and Arrays Using Converging Oxide Ringlets,xe2x80x9d by Corzine et al. This approach has the advantage of a relatively simple wafer fabrication process and suitable for low-cost mass production. This planar structure has proven to be able to provide sufficient performance for current 1 Gb/s to 2 Gb/s data transmission rates. However, due to the fact that, in order to connect the oxide fronts originated from adjacent oxidation holes (or other geometry) to form a closed perisphere oxide aperture, the oxidation process is typically long and thus the oxidation area is large which may limit its performance at higher data transmission rates.
Another planar-type VCSEL is described in a paper entitled, xe2x80x9cVCSEL Based Modules for Optical Interconnects,xe2x80x9d by Strzelecka, E. M., Morgan, R. A., Liu, Y., Walterson, B., Skogen, J., Kalweit, E., Bounak, S., Chanhvongsak, H., Marta, T., Skogman, D., Nohava, J., Gieske, J., Lehman, J., Hibbs-Brenner, M. K, Proceedings of the SPIExe2x80x94The International Society for Optical Engineering, Vol. 3627, pages 2-13, 1999. This approach uses multiple trenches or segments. Unfortunately, this approach does not adequately address parasitic capacitance issues. Consequently, this approach may suffer in performance especially at high data rates.
As the bit rates of data transmission increase to greater than two gigabits per second and beyond, new design considerations and mechanisms are required to achieve these types of data transmission speeds. Unfortunately, the prior art approaches do not identify or address these design considerations for high-speed VCSEL design. The inventors of the present invention have identified the parasitic capacitance of the VCSEL as an important design consideration for those devices operating at greater than two gigabits per second and especially for devices designed to operate at greater than ten gigabits per second.
Unfortunately, the prior art approaches do not provide any mechanism to adequately address and reduce the parasitic capacitance of VCSEL structures. Consequently, the prior art structures may suffer from high parasitic capacitance that can limit the VCSEL""s speed performance at the high-speed transmission rates given above.
Based on the foregoing, there remains a need for a high speed vertical cavity surface emitting laser that overcomes reduces the parasitic capacitance of the device and at the same time overcomes the disadvantages set forth previously.
In one embodiment, the present invention is a VCSEL with a nearly planar top surface on which the top electrode is disposed. A VCSEL according to the present invention includes a top electrode that is preferably a ring contact, a top mirror having a top surface, a light generation region, and a bottom mirror for reflecting light toward the top mirror. At least one of the mirrors includes a plurality of planar electrically conducting layers having different indices of refraction. At least one aperture-defining layer having an isolatable material is provided in at least one of the bottom mirror structure and the top mirror structure. The isolatable material can be oxidized, etched, or oxidized and then selectively etched, to form an insulating region that has an aperture-defining surface for defining at least a portion of an aperture.
A single trench that has a continuous geometry for reducing the parasitic capacitance is etched down from the top surface of the VCSEL through or beyond those layers having the isolatable material. At least one of these isolatable layers is used for an aperture-defining purpose. The trench can be utilized to expose the isolatable layer to an isolating agent (thereby converting the isolatable material to an insulating region), thereby oxidizing and/or etching the isolatable layer. The partial isolation of the layer converts the layer to one having a conducting region surrounded by an electrically insulating region, the conducting region being positioned under the top electrode.
Preferably, the aperture-defining layer has a conducting region, an insulating region having an aperture-defining surface for defining the conducting region, and a single trench adjacent to the insulating region for use in generating the insulating region. The trench has a continuous geometry for reducing the parasitic capacitance of the VCSEL.
In an alternative embodiment of the present invention, a ring shape conductive contact is replaced with a transparent disk-shape conductive contact. The transparent disk-shape conductive contact features a larger contact area, as compared to the first embodiment, in order to reduce the contact resistance. Furthermore, this embodiment allows an optimization of oxidization depth, thereby reducing the parasitic capacitance.
According to another aspect of the present invention, a VCSEL structure with or without a near planar top surface can be fabricated to include a plurality of isolatable layers where each layer has an insulating region (e.g., an oxide ring). These multiple insulating regions provide a mechanism for reducing the product of the total parasitic capacitance and the differential resistance at the VCSEL""s bias point.
According to yet another aspect of the present invention, a VCSEL structure with or without a near planar top surface can be fabricated to include a capacitance-reducing implantation region that can serve as another mechanism for reducing the product of the total parasitic capacitance and the differential resistance at the VCSEL""s bias point.
According to another aspect of the present invention, a VCSEL structure with or without a near planar top surface can be fabricated to include an insulating layer (e.g., a low k dielectric layer) disposed on at least a portion of the near planar top surface of the device. A conducting material for electrically coupling a bond pad to an emitting area is then deposited on at least a portion of the insulating layer. The insulating layer serves as a mechanism for reducing the parasitic capacitance due to the contact between the semiconductor surface and a conductive contact.